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| Kun-Lin Tsai, Szu-Wei Chang, Feipei Lai, and Shanq-Jang Ruan, "A Low Power Scheduling Method using Dual Vdd and Dual Vth," in Proceeding of IEEE International Symposium on Circuit and Systems, May 2005. |
| Kun-Lin Tsai, Shanq-Jang Ruan, Li-Wei Chen, Feipei Lai, and Edwin Naroska, "Low Power Dynamic Bus Encoding for Deep Sub-micron Design," in Proceeding of 3rd International IEEE Northeast Workshop on Circuits & Systems, June 2005. |
| Shanq-Jang Ruan, Kun-Lin Tsai, Edwin Naroska, and Feipei Lai, "Bipartition and Encoding in Low Power Pipeline Circuits," ACM Trans. on Design Automation of Electronic Systems, Vol. 10, No. 1, pp. 24-32, Jan 2005. |
| Yen-Jen Chang, Chia-Lin Yang, Feipei Lai, "Value-Conscious Cache: Simple Technique for Reducing Cache Access Power," in IEEE Proceeding of Design, Automation and Test in Europe Conference and Exhibition, Feb 2004. |
| Chuan-Heng Hsiao, Ming-Long Lee, Yuan-Chung Shen, and Feipei Lai, "A Design of Small-area Automatic Wheelchair," in Proceeding of IEEE International Conference on Networking, Sensing and Control, 2004. |
| Jen-Chiun Lin, Chien-Hua Tzeng, Feipei Lai, and Hung-Chang Lee, "Optimizing Centralized Secure Group Communications with Binary Key Tree Recomposition," in IEEE Proceeding of International Conference on Advanced Information Netowrking and Applications, 2004. |
| Bor-Shyh Lin, Bor-Shing Lin, Fok-Ching Chong, and Feipei Lai, "Adaptive interference cancel filter for evoked potential using high-order cumulants," In IEEE Proceeding of International Conference of Engineering in Medicine and Biology Society, Sept. 2004. |
| Yen-Jen Chang, Feipei Lai, and Chia-Lin Yang, " Zero-aware Asymmetric SRAM cell for Reducing Cache Power in Writing Zero," IEEE Transitions on Very Large Scale Integration (VLSI) Systems, Aug. 2004. |
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